Maybe many customers want to know: why is the cost of unlocking IC so high? How do we unlock IC? Because there are thousands of IC models, each type of IC’s internal structure and wafer situation is different. Our company has invested a lot of labor cost, money cost, and high-end and expensive equipment for every IC solution. Many IC unlocking engineers have different experiences in different ways! That’s why it’s costly to crack.
With the acceptance of chip model identification and chip unlock by customers, the original chip will be damaged. What cannot return it in most cases after we have worked on the chip.
This technology typically monitors the analog characteristics of all power and interface connections of the processor during regular operation at a high time resolution. It implements attacks by monitoring its electromagnetic radiation characteristics because it is an active electronic device when it executes different instructions. The corresponding power consumption changes accordingly;
thus, What can obtain specific critical information in the MCU by analyzing and detecting these changes using special electronic measuring instruments and mathematical-statistical methods.
This principle is used when an RF programmer can read directly from an older type of encrypted MCU.
Probe technology exposes the internal connection of the chip directly and then observes, manipulates, and interferes with the single-chip computer to achieve the attack’s purpose.
Fault Generation Techniques
The chip technology uses abnormal working conditions to make the processor fail and then provides additional attack access. The most widely used means of fault generation include voltage and clock shocks. Low and high voltage attacks can prevent the protection circuit from working or force the processor to perform incorrect operations. Clock quick jumps may reset the protection circuit without damaging the protected information. Power and clock transient jumps can affect the decoding and execution of a single instruction in some processors.
IC reverse analysis / reverse design:
Due to the domestic research in the field of analog integrated circuit design is relatively weak, professional circuit board chip decryption, chip reverse analysis has become an effective way for most analog integrated circuit engineers to accumulate experience based on actual analog circuits. IC reverse design has also become an effective means to promote the progress of domestic integrated circuit design.
In IC reverse analysis and design services, IC crack service providers mainly provide the following services:
We use FIB to modify the chip circuit;
It can enable the chip designer and Shen OROD to test the chip problems to verify the design scheme more quickly and accurately to find the problem’s crux. FIB can also provide some samples and engineering chips before the mass production of the final product. Using these samples can speed up the time to market of the terminal effect. Using FIB to modify the chip can reduce the number of unsuccessful design modifications, shorten the development time and cycle. For customers who do IC unlock, What can achieve the effect of decryption by modifying the circuit.
Reverse and safety analysis of MCU, CPLD, FPGA, etc
Analyze and test MCU, CPLD, FPGA, and other chips, do reverse code extraction, and security vulnerability test analysis.
FIB is used to make cross-section fault at a specific IC chip position, and the cross-section structure and material of material are analyzed at a fixed point. It can help IC designers to analyze the performance of IC design.
Network list/circuit diagram extraction and logic function analysis
In chip reverse engineering, netlist/circuit diagram extraction is very important. The quality and speed of netlist extraction directly affect the work of finishing, simulation, and LVS. In the long-term technical research, OROD has successfully summed up a set of feasible specifications and methods;
which can extract the netlist of various circuits with high quality and high speed.
After the extraction of the netlist, it is often necessary to sort out the circuit. A flattened circuit is sorted out hierarchically to form a hierarchical structure of the circuit to understand the designer’s design ideas and skills, and at the same time, to find the netlist errors. Shenzhen OROD can fully understand the chip designer’s design ideas and abilities and improve its design ability based on analyzing and summarizing the progressive design ideas.
The layout design is the physical realization of circuit logic, and it is also the chip logic layer editor. Based on the reverse design, Shenzhen OROD provides various design services such as layout extraction, process library replacement, target process modification, DRC check, and LVS check.
Logic layout verification
To ensure the integrity of the design process,
OROD mainly provides FPGA verification, logic simulation verification, and LVS verification services for chip netlist data and layout data.